Building a Scientific Calculator from Scratch: An FPGA Journey

The creation of a scientific calculator is often viewed as a solved problem in the era of ubiquitous smartphones and powerful microcontrollers. However, for the hardware enthusiast, the challenge lies not in the utility of the device, but in the architectural purity of its implementation. One such project, documented by zdw, takes this challenge to the extreme: designing a scientific calculator from the ground up using a Field Programmable Gate Array (FPGA).

This project is not merely about assembling components, but about recreating the spirit of vintage computing—specifically the Binary Coded Decimal (BCD) architecture used by classic HP calculators. By eschewing standard floating-point units in favor of a system where every decimal digit is represented as a 4-bit nibble, the project ensures perfect decimal accuracy and eliminates the common conversion errors associated with binary floating-point arithmetic.

The Path to Implementation

Every complex hardware project begins with a phase of "pathfinding." As the author notes, this is the often-undocumented stage of trial and error where designs are prototyped and discarded before a final architecture is settled upon. For this calculator, pathfinding led to the realization that complex functions like tan, ln, exp, and sqrt could be implemented using only basic addition, subtraction, and multiplication, provided the right numerical tricks were applied.

To ensure the hardware's reliability, a verified reference implementation was created in C++. This allowed the author to test the hardware against thousands of known-good vectors, ensuring that the final device could maintain accuracy up to 16 decimal digits.

A Unified Testing Framework

One of the most significant hurdles in FPGA development is testing hardware that does not yet physically exist. To solve this, a comprehensive framework was developed to run a single Verilog source across four distinct environments:

• ModelSim: Used for signal-level simulation.
• Verilator: Used for cycle-accurate C++ modeling.
• Qt: Provided a desktop prototype with a debugger console.
• WebAssembly: Allowed the application to run in a browser without changing the RTL (Register Transfer Level) code.

This multi-tiered approach allowed for rapid iteration, moving from high-level software simulation to cycle-accurate hardware modeling before a single PCB was ever ordered.

Designing a Custom CPU for BCD

Because general-purpose CPUs are not designed for nibble-addressable memory or the specific needs of a 16-digit BCD mantissa, the project required the design of a custom CPU. The resulting architecture features:

• 12-bit fixed-length instructions.
• A Harvard memory model.
• 14 ALU operations, including BCD-adjust instructions inspired by the Intel 8086.

This custom ISA (Instruction Set Architecture) was refined iteratively. By writing microcode and testing it in Verilator, the author could identify flaws in the ISA and adjust the hardware logic accordingly.

From Microcode to Physical Hardware

With the CPU architecture finalized, the focus shifted to microcode—the low-level instructions that control the CPU's operations. This included implementing number input, display formatting, and arithmetic functions. To simplify complex operations (like $y^x$), a small scripting interpreter was layered on top of the microcode, allowing complex functions to be collapsed into a few lines of tokens.

The transition to physical hardware happened in stages. It began with a $5 EP2C5 development board connected to a keypad and OLED display via ribbon cables. The final iteration evolved into a custom PCB with the FPGA soldered directly, a 3D-printed enclosure, and color-coded keycaps following the classic HP yellow-and-red convention.

Chasing Precision and Final Reflections

Initial versions of the project achieved accuracy to roughly 12 digits, but a 16-digit BCD machine demands absolute precision. A 2025 rewrite of the arithmetic engine introduced:

• Guard digits and sticky bit tracking to prevent rounding errors.
• Banker's rounding for improved statistical accuracy.
• A full trigonometric suite and ten STO/RCL memory registers.
• A hardware LFSR (Linear Feedback Shift Register) for random number generation.

In the end, the entire system—CPU, arithmetic engine, and peripherals—occupied only 1,593 logic cells, utilizing approximately 35% of a small, inexpensive FPGA. While the author admits the physical tactile feel of the keypad didn't quite match the vintage HP originals, the project serves as a masterclass in the full-stack journey from logic gates to mathematical primitives.