Building a Nibble-Oriented CPU for a Scientific Calculator

The quest to understand how classic scientific calculators functioned at the gate level often leads to a fascinating intersection of computer architecture and mathematics. In a recent project by developer gdevic, this curiosity culminated in the creation of a fully functional scientific calculator powered by a custom-designed, nibble-oriented CPU written in Verilog.

Unlike modern general-purpose processors, this CPU was not designed for efficiency in general computing, but rather for the specific requirements of decimal arithmetic. By rethinking the fundamental data width of the processor, the creator has built a system that mirrors the logic of high-end scientific calculators from the golden age of computing.

The Architectural Choice: Why Nibbles?

Most modern CPUs are byte-oriented, meaning the smallest addressable unit of memory is 8 bits. However, for a scientific calculator, the most efficient way to store numbers is often Binary Coded Decimal (BCD), where each decimal digit (0-9) is represented by a 4-bit nibble.

As the author explains, using a standard byte-oriented CPU like a Z80 or 6502 for BCD operations is a constant struggle, as the hardware "fights" the layout of the data. To solve this, gdevic designed a custom CPU where 4 bits is the natural data width and memory is nibble-addressable. This alignment ensures that the hardware is natively optimized for decimal digits, eliminating the overhead associated with packing and unpacking bytes.

Technical Specifications of the Custom CPU

The project is a comprehensive exercise in hardware and software co-design. The CPU architecture includes several sophisticated features:

• Harvard Architecture: The system separates instruction memory from data memory, allowing for simultaneous access to both, which is improves throughput.
• 12-bit ISA: A custom Instruction Set Architecture designed specifically for the calculator's operations.
• 8-state Execution FSM: A finite state machine that manages the CPU's execution cycle.
• Hardware Stack Guard: A dedicated mechanism to prevent stack overflows, featuring a "FAULT" state specifically for microcode debugging.

Beyond the CPU: The Full System Stack

Building the processor was only the first step. To make the calculator functional, the author developed a complete ecosystem of tools:

Mathematical Implementation

To handle trigonometric and transcendental functions, the CPU utilizes CORDIC (Coordinate Rotation Digital Computer). This implementation was verified to 14 significant digits of accuracy, providing the professional-grade precision expected of a scientific calculator.

Tooling and Simulation

One of the the most impressive aspects of the project is the versatility of the implementation. Using a combination of Verilator and the Qt framework, the same Verilog source code can be deployed in multiple environments:

• Physical Hardware: Running on a custom PCB with a battery and charging circuit.
• Desktop GUI: A debugger that allows users to inspect registers and set breakpoints.
• WebAssembly: A version that runs directly in the browser, allowing users to interact with the "hardware" and its microcode via a simple UI shell.

Software Layer

To bridge the gap between hardware and microcode, the author wrote a two-pass assembler in Python (approximately 700 lines) and implemented a scripting language on top of the microcode. This allows for the addition of new functions without requiring changes to the underlying hardware logic.

Community Insights and Reflections

The project resonated strongly with the hardware community, evoking nostalgia for the legendary HP calculators and their use of Reverse Polish Notation (RPN). One user noted the distinct feeling of owning an HP calculator in the 70s and 80s, where the physical construction and accuracy were paramount.

From a technical perspective, the project also highlighted the challenges of working with non-standard architectures. One contributor mentioned the difficulty of using tools like Ghidra for reverse engineering, noting that "attempting to shoehorn [non-byte aligned memory regions] into ghidra produces not great results."

By returning to the fundamentals of gate-level design and BCD arithmetic, this project serves as a masterclass in how specialized hardware can be perfectly tailored to a specific mathematical purpose.